1. Field of the Invention
This invention relates to electronic devices such as integrated circuits, hybrid circuits and multi-chip integrated circuit modules and in particular to low cost, high performance packages with enhanced thermal capabilities for the packaging of integrated circuit devices. More particularly, the invention relates to ball grid array packages incorporating an integral thermal conductor having an exposed outer surface.
2. Prior Art
Early generations of integrated circuit packages mounted the integrated circuit chip in a metal can or between a ceramic lid and base. Both ceramic and metal packaging provided excellent thermal properties. However, these packaging methods also necessitated expensive and time consuming manufacturing techniques.
As semiconductor production volumes grew, more cost effective packages were developed. The most notable was the plastic molded package. In particular, the plastic molded ball grid array package, such as described in U.S. Pat. No. 5,241,133 issued to Mullen III et al., on Aug. 31, 1993, and assigned to Motorola, Inc., has proven to be a promising packaging technique in terms of cost and input/output capability. Ball grid array packages are desirable because ball grid array packages eliminate difficulties in surface mounting prior art fine pitch plastic packages. Ball grid array packages also eliminate the need to route package leads to the outer edges of the integrated circuit package. Ball grid array packages also allow for smaller packages and very close spacing of packages mounted to the same printed circuit board. Finally, ball grid array packages provide shorter interconnect lengths which results in improved electrical performance. The advantages described above, along with the low cost of ball grid array packaging, make ball grid array packages an ideal packaging format for many integrated circuit applications. However, prior art ball grid array packages suffer from relatively poor heat dissipation characteristics. This means that this otherwise highly useful form of packaging can be impractical for use with newer generations of integrated circuit chips which use more power and thus generate considerable heat.
In recent developments, some ball grid array packages have been fitted with a separately formed and fitted heat sink in an attempt to improve the heat dissipation characteristics of the package. However, these ball grid array packages are difficult and expensive to manufacture. Further, the resulting packages are relatively thick and heavy which makes these ball grid array packages unsuitable for use in many electronics applications which require small size and light weight.
FIG. 1 is a cross-sectional view of a prior art ball grid array package 100 with integrated circuit chip 102. Prior art ball grid array package 100 includes a heat sink 104 which is attached to an interconnection substrate 108 with an adhesive preform 125. Heat sink 104 is typically a 1.0 to 1.6 millimeters thick metallic plate. As a result the overall package thickness 109 of prior art ball grid array package 100 is typically 2.3 to 3.7 millimeters.
While prior art ball grid array package 100 represents an improvement over some prior art ball grid array packages, at least in terms of heat dissipation, prior art ball grid array package 100 still suffers from several major drawbacks.
First, heat sink 104 only partially covers the outer surface 108A of interconnection substrate 108. The result of this configuration is that the heat generated by integrated circuit chip 102 is centralized within prior art ball grid array package 100 at the location of heat sink 104. Further, as heat sink 104 absorbs heat generated by integrated circuit chip 102, heat sink 104 expands. Since heat sink 104 is not linearly co-extensive with interconnection substrate 108, i.e., heat sink 104 only partially covers interconnection substrate 108, the expansion of heat sink 104 creates uneven stress on interconnection substrate 108 and prior art ball grid array 100. As a result of this uneven heat distribution and stress, the electrical connections between prior art ball grid array package 100 and a printed circuit mother board (not shown) often fail due to thermally induced stress cracks or metal fatigue. The electrical connections made by interior solder balls 118A are particularly vulnerable to thermal stress failure. These failures are a major problem because the electrical connections made by solder balls 118 and 118A allow prior art ball grid array package 100, and integrated circuit chip 102, to be utilized as part of a larger electronic structure and are therefore vital to the use of ball grid array packages in electronic systems using printed circuit boards.
Furthermore, as a result of the fact that heat sink 104 only partially covers interconnection substrate surface 108A, adhesive preform 125 is a weak point in the structure and the heat sink 104/substrate 108 junction 107 often provides a shortened path for contamination and moisture to enter the package. This type of contamination degrades the performance of integrated circuit chip 102 and compromises package reliability.
Prior art ball grid array package 100 is also complicated and expensive to manufacture because the process of attaching heat sink 104 requires complex individual unit positioning fixtures and tooling for centering heat sink 104, as well as a pressurized curing process. As a result, prior art ball grid array package 100 is typically produced as an individual unit because the heat sink 104 of prior art ball grid array package 100 does not lend itself to panel or strip format production. This adds considerably to the cost of producing prior art ball grid array package 100 and is a relatively time consuming and inefficient process.
Additionally, prior art ball grid array package 100 is a heavy and volume consuming integrated circuit package because heat sink 104 must be relatively thick (typically 1.0 to 1.6 millimeters) to present sufficient surface area for heat dissipation. Further, the minimum thickness of interconnection substrate 108 is limited to approximately 0.60 to 1.0 millimeters. This is because thinner interconnection substrate structures tend to warp causing difficulties in making electrical connections between prior art ball grid array package 100 and the mother board (not shown). The resulting thickness 109 of prior art ball grid array package 100 is typically 2.3 to 3.7 millimeters.
The weight and thickness of prior art ball grid array package 100 is particularly problematic in view of the increased demand for thinner and lighter packages which is driven by the "lap-top" "notebook" and "pocket" computer markets as well as cellular phones, hand held video games, and numerous other size and weight conscious applications which are coming onto the market every day.
It is therefore highly desirable to provide a lower cost ball grid array package, and method for creating and mass producing the same, which has superior heat dissipation characteristics, small size, light weight, and avoids the structural problems associated with prior art ball grid array packages.